Nonvolatile memory, such as, for example, flash memory, is utilized in a wide variety of electronic devices and applications. In order to increase information storage density, flash memory has evolved from single-level-cell (SLC) memory, wherein each of the memory cells contain a single binary bit of information (e.g., two levels of charge store) to multiple-level-cell (MLC) memory, wherein each of the memory cells contain a plurality of bits of information. The present state of the art is MLC memory wherein each cell is capable of storing two bits of information represented in one of four discrete charge levels within the cell.
Unfortunately, however, to discriminate between multiple discrete charge levels stored within multi-level flash memory cells, sense amplifiers used in the memory for reading the respective states of the cells therein, are either many times larger than for single-level flash memory, or take significantly longer time to discriminate the multiple charge levels. Sense amplifiers are typically placed on column pitch within a given memory, so there are many sense amplifiers within the memory. Each column or small group of multiplexed columns in the memory typically has its own sense amplifier(s). The problem of discriminating between multiple discrete charge levels stored within the cells becomes particularly acute as the number of bits stored within a single memory cell increases.
Because multi-level flash memory has, thus far, been limited to two bits per memory cell, this discrimination problem has been relatively manageable with only limited impact on the size and/or performance of the memory. Conventional approaches for determining the stored state of a two-bit flash memory cell involve employing multiple (e.g., three) sense amplifiers to discriminate between the four discrete charge levels indicative of the four states of the cell. Alternatively, single sense amplifiers have been used to iteratively discriminate between the four charge levels. In this instance, a three-loop iteration is required.
Another problem in high-density flash memory is that as the number of bits stored within a single memory cell increases, the measurable difference between respective charge levels decreases, thereby increasing the likelihood of an error in reading the state of the memory cell. For example, while a two-bit cell must store four discrete charge levels, a four-bit cell must store 16 discrete charge levels. The difference between successive charge levels for a four-bit memory cell will be significantly smaller compared to a two-bit memory cell. Consequently, more sophisticated error correction schemes are required to detect and correct erroneous bits of stored data using conventional methodologies.
Accordingly, there exists a need for techniques for increasing data storage density in a flash memory device which do not suffer from one or more of the above-described problems associated with conventional memory devices.